1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) and a data writing method therefor.
2. Related Background Art
In recent years, an MRAM which has highly densely integrated magnetic substances on a substrate as memory cells, and which has nonvolatile characteristics, a high speed operation and repetition resistance of magnetic recording, has been expected as a next generation memory.
FIGS. 7A and 7B are perspective views each useful in explaining a basic structure and an operation of a memory cell of an MRAM.
As shown in FIG. 7A, an MRAM cell includes a pinned layer 12 made of a ferromagnetic film and having a fixed magnetization direction, an insulating film 13 and a data storage layer 14 made of a ferromagnetic film. The MRAM cell is provided between a lower wiring 11 and an upper wiring 15.
FIG. 7B is a perspective view useful in explaining the operation for writing and reading out data to and from the memory cell shown in FIG. 7A.
The storage of data is carried out by utilizing the “magneto-resistance effect” in which a resistance value of the insulating film is changed by 30 to 40% between a state in which directions of magnetization of the pinned layer 12 and the data storage layer 14 are “parallel” to each other (corresponding to data 0) and a state in which directions of magnetization of the pinned layer 12 and the data storage layer 14 are “anti-parallel” to each other (corresponding to data 1). For this storage, a direction of magnetization of the data storage layer 14 is changed by an external magnetic field generated by causing a predetermined current through the upper wiring 15 and the lower wiring 11 to thereby store binary digit data, for example.
The operation for reading out data from a memory cell is as follows: A predetermined potential difference is applied across the upper wiring 15 and the lower wiring 11 to cause a tunneling current 16. This tunneling current 16 penetrates through the pinned layer 12, the insulating layer 13 and the data storage layer 14 to be caused to flow from the lower wiring 11 to the upper wiring 15. Thus, data is read out from the memory cell. That is to say, the resistance value of the insulating film 13 is changed due to the tunnel magneto-resistance effect when the directions of magnetization of the two ferromagnetic layers 12 and 14 sandwiching therebetween the insulating layer 13 are parallel or anti-parallel to each other. Then, this change in current is detected to thereby read out data stored in a memory cell to the outside.
FIG. 8 is a schematic view useful in explaining a write operation of the MRAM in which the memory cells shown in FIGS. 7A and 7B are arranged in an array.
Here, description will hereinbelow be given with respect to a case where data is written to a memory cell MC. Predetermined currents (write currents C1 and C2) are selectively caused to flow through a word line W112 and a bit line B152 at the time when data is intended to be written to the memory cell MC to regulate magnetic domains (domains) of the data storage layer of the memory cell MC in one direction by utilizing a composite magnetic field M12 obtained by composing magnetic fields (magnetic fields M1 and M2) induced in the circumference of the wirings. Thus, the operation for writing data to the memory cell MC is realized.
On the other hand, for storage of inverted data in the memory cell MC, a direction of a current to be caused to flow through one of the word line W112 and the bit line B152, e.g., the bit line B152 is selectively inverted with respect to the above-mentioned case of the operation for writing data to the memory cell MC. Thus, a direction of the magnetic field M2 is changed by 180 degrees to change a direction of the composite magnetic field M12 by 90 degrees, whereby the domains of the data storage layer in the memory cell MC are forcibly inverted. As a result, “parallelism” and “anti-parallelism” in the direction of the domains of the pinned layer and the data storage layer can be realized by utilizing the external magnetic field.
As described above, in the MRAM memory cell array, a current caused to flow through a memory cell at a crossing point between the selected word line and bit line is detected to judge a storage state. However, if a scale of a memory cell array itself is increased, then wiring resistances and wiring capacities of word lines and bit lines are increased according. As a result a value of a detected current caused to flow when data is read out from a memory cell becomes small or a delay in response when data is read out therefrom is increased.
In particular, since a memory cell is constituted by an insulating film, which is about 2 nm thick, sandwiched between ferromagnetic films of two layers, for a main component of a wiring capacity, a capacity due to a memory cell connected to wirings is larger than that of the wirings themselves. Thus, if the number of memory cells connected to wirings is increased, then the wiring capacity is increased in proportion thereto.
In order to avoid such a problem, there have conventionally been taken measures that, for example, an upper limit is set to a wiring resistance so that a current level when reading out data from a memory cell does not become smaller than a predetermined value, a wiring length is limited in order to avoid an increase in wiring capacity to limit a scale of a memory cell array, and so forth.
However, as the MRAM capacity is increased, a scale of the memory cell array has to be increased. Thus, this problem has gradually become important.
In order to cope with such a problem, a proposal of dividing a memory cell array has been made.
FIG. 9 schematically shows such a configuration, and is a circuit diagram showing a sub-memory cell array constituted by sub-word lines SW1 to SWm and sub-bit lines SB1 to SBn.
The sub-word lines SW1 to SWm constituting the sub-memory cell array are connected to main word lines W1 to Wm through sub-word line selecting transistors WT1 to WTm, respectively. The sub-bit lines SB1 to SBn are connected to main bit lines B1 to Bn through sub-bit line selecting transistors BT1 to BTn, respectively. In such a manner, the memory cell array is configured in the form of a hierarchical structure of the main bit lines and the main word lines, and the sub-bit lines and the sub-word lines (refer to JP 2002-170379 A (FIG. 1) for example).
As described above, the MRAM has high performance such as the high speed rewriting and reading. However, on the other hand, since at the time when data is intended to be written, currents are caused to flow through corresponding ones of wirings to generate induced magnetic fields, relatively large write currents, i.e., write currents of several milliamperes are required per memory cell. If a method of dividing a conventional memory cell array into blocks is introduced in order to avoid the above-mentioned problem, there may be encountered a problem as will be described below. The division of the cell array, as described above, adopts a hierarchical structure having the main bit lines and the main word lines distributed so as to cover the whole cell array, and the sub-bit lines and the sub-word lines distributed only within each of the blocks (sub-cell arrays). Then, normal MOS transistors are required as switching elements for changing the main bit lines and the main word lines over to the sub-bit lines and the sub-word lines. Such switching elements are formed in each of the blocks obtained by the division to change the main bit lines and the main word lines over to the sub-bit lines and the sub-word lines, respectively. In the MRAM, an ability to cause a current at a milliampere level to flow is required for the MOS transistor as the switching element in correspondence to a current when data is written. As is well known, a MOS transistor can cause a current a magnitude of which is proportional to a width (W) of a gate electrode, but is inversely proportional to a length (L) thereof to flow therethrough. Hence, if a size ratio of a length to a width of the gate electrode is determined, and moreover, certain design conditions are determined for the MOS transistor as the switching element, then absolute values of a length and a width of the gate electrode which are required will be inevitably determined therefrom. Usually, the ratio of W to L needs to be set to fall within the range of about 10 to 50 in order to cause a current of several milliamperes to flow. Thus, for example, if a MOS transistor device with L of 0.2 μm is intended to be formed, then W must be 2 to 10 μm.